1. Field of the Invention
The present invention relates to integrated circuits. More specifically, the present invention relates to a method and an apparatus for using extra communication bits to refresh receiver circuits without exposing the refresh mechanism to the architecture and without suffering a bandwidth penalty.
2. Related Art
Typical communication systems can be decomposed into three parts: a driver, a channel, and a receiver. Each part has at least one and often many bits running in parallel. For example, an on-chip bus from a memory to an arithmetic unit can be a 64-bit system, with 64 drivers, a 64-bit wire bus as the channel, and 64 receivers. In another example, an optical system between switch line cards can be a 4-bit system, with 4 lasers, a single optical fiber channel with four wavelengths, and 4 optical receiver diodes.
In communication systems using capacitively-coupled or inductively-coupled inputs (such as those based on Proximity Communication) or on-chip capacitive or inductive coupling, the receiver's inputs need to be set up (or biased) to a preferred mode of operation. This may be performed, for example, to set the receiver threshold between the digital values of “0” and “1”, to increase its signal sensitivity, to decrease its delay, or to reduce its power consumption.
This biasing, or refreshing, can be performed periodically. During this refreshing, the inputs get pre-charged to the right bias before each data item is received, or post-charged to the right bias after each data item is received. However, such pre/post-charge circuits tend to be power-inefficient because they typically operate on every single data item. Furthermore, they typically limit data rates because the receiver has only half the bit period to actually receive the data; the other half of the bit period is spent refreshing. Finally, refreshing every cycle is often unnecessary, as the bias may degrade only as a result of secondary effects such as leakage. Thus, bias schemes that operate more infrequently can be desirable.
Biasing a receiver infrequently is most simply accomplished by building an “every-cycle” bias circuit and squelching the bias circuit most of the time. However, this raises the problem of architectural exposure. In this example, higher-level control structures need to be aware of when and how long the channel refreshes. In other words, a system designed to refresh after 100 data items requires the next bits to pause while the system refreshes all of its receivers. Moreover, this increases complexity in the control mechanism, and it costs bandwidth. For example, if the refresh takes the same time as ten communicated data items, the bandwidth cost for refresh is 10%. Additionally, some refreshing (to establish a threshold voltage for a non-DC-balanced data stream, for instance) may require transmitting a special mid-level signal during the refresh, making it difficult to refresh in a single bit period or less.
Hence, what is needed is a bias mechanism that does not suffer from the problems described above.